module dec7seg(data, LED); input [3:0] data; output [7:0] LED; wire [3:0] data; reg [7:0] LED; always @(data) case (data) 4'd0: LED = 8'b11000000; 4'd1: LED = 8'b11111100; 4'd2: LED = 8'b10010010; 4'd3: LED = 8'b10011000; 4'd4: LED = 8'b10101100; 4'd5: LED = 8'b10001001; 4'd6: LED = 8'b10000001; 4'd7: LED = 8'b11011100; 4'd8: LED = 8'b10000000; 4'd9: LED = 8'b10001000; default: LED = 8'bxxxxxxxx; endcase endmodule