module dcount(CLK, RES, LED); input CLK, RES; output [7:0] LED; wire CLK, RES; reg [7:0] LED; reg [3:0] count; always @(posedge CLK or negedge RES) if (RES == 1'b0) count = 4'd0; else if (count == 4'd9) count = 4'd0; else count = count + 4'd1; always @(count) case (count) 4'd0: LED = 8'b11000000; 4'd1: LED = 8'b11111100; 4'd2: LED = 8'b10010010; 4'd3: LED = 8'b10011000; 4'd4: LED = 8'b10101100; 4'd5: LED = 8'b10001001; 4'd6: LED = 8'b10000001; 4'd7: LED = 8'b11001100; 4'd8: LED = 8'b10000000; 4'd9: LED = 8'b10001000; default: LED = 8'bxxxxxxxx; endcase endmodule