module shift(CLK, RES, Q); input CLK, RES; output [3:0] Q; wire CLK, RES, EN; reg [3:0] Q; reg [11:0] scale; parameter SCALECNT = 12'd4000; always @(posedge CLK or negedge RES) if (RES == 1'b0) scale <= 12'd0; else if (scale == (SCALECNT - 1)) scale <=12'd0; else scale <= scale + 12'd1; assign EN = scale == (SCALECNT - 1); always @(posedge CLK or negedge RES) if (RES == 1'b0) Q <= 4'b0001; else if (EN == 1'b1) Q <= {Q[2:0],Q[3]}; endmodule